1. Technical Field
The present invention generally relates to integrated circuits and in particular to leakage current in integrated circuits. Still more particularly, the present invention relates to compensation of leakage current in integrated circuits.
2. Description of the Related Art
In Integrated circuit (IC) fabrication technology, lower threshold voltages and smaller transistor geometry result in higher leakage current, which is defined as the current passing through a transistor when it is turned off. Threshold voltage refers to the voltage at which transistors turn on. Leakage current consumes power and reduces standby time for portable devices that use battery power. Consequently, reducing leakage current without sacrificing too much performance is one of the major challenges in IC designs. Leakage current is more problematic as IC circuits become smaller. This is because leakage current increases at a high rate as transistor size decreases.
Increasing the sub-threshold leakage current with process scaling has forced designers to upsize the keeper (which provides a stabilizing effect) in dynamic circuits in order to achieve an acceptable robustness in the worst case leakage corner. Various studies have shown that there is a wide range of variation in die-to-die Negative Field Effect Transistor (NFET) leakage. This variation indicates that a large number of low leakage dies suffer from the performance loss due to an unnecessarily over sized keeper. Unfortunately, the excess leakage dies still do not satisfy the robustness requirements with a keeper sized for the faster corner leakage. This inability to satisfy performance requirements reveals the drawbacks of a conventional keeper used under a wide range of inter or intra-die variation.
A Process-Compensation-Dynamic (PCD) circuit technique has been proposed to improve overall robustness and delay variation spread by (a) restoring robustness of worst-case leakage dies and (b) improving performance of low-leakage dies. Unlike prior fixed-strength keeper techniques, the PCD circuit technique utilizes a programmable keeper, which is optimally programmed based on the respective die leakage. In the PCD implementation, a digitally programmable 3 bit keeper is applied on an 8-way register file's Local Bitline (LBL). Each of the three binary-weighted keepers, with respective widths W, 2 W and 4 W, may be activated or deactivated by asserting pre-coded 3-bit globally routed control signals. These global signals need to be incorporated with the die leakage statistics, and are incorporated with manually conducted off-line sampling and statistical procedures. Thus, the use of these globally-routed control signals is usually costly and time consuming.